1. Field of the Invention
The present invention relates to a semiconductor circuit device and, more particularly, to a semiconductor circuit device having an input protection circuit protecting an input circuit against a surge voltage such as static electricity applied to an input pad. More specifically, the present invention relates to a structure for improving surge resistance of a multipower source semiconductor circuit device to which a plurality of power supply voltages are applied externally.
2. Description of the Background Art
FIG. 1 schematically shows a configuration of an signal input portion of a conventional semiconductor circuit device. Referring to FIG. 1, the conventional semiconductor circuit device includes an input circuit 2 receiving a signal applied to input pad 1 and generating an internal signal, and an internal circuit 3 performing a prescribed process in accordance with the internal signal applied from input circuit 2. Input circuit 2 operates using a power supply voltage Vddi on a power supply node PS1 and the ground voltage GND as two operational power source voltages, and converts an amplitude of the input signal applied to input pad 1 to the level of the power supply voltage Vddi. Internal circuit 3 operates using a power supply voltage Vdd on a power supply node PS2 and the ground voltage GND as two operational power source voltages.
The semiconductor circuit device further includes a diode type input protection circuit 2 for protecting input circuit 2 against a surge voltage applied to input pad 1. Diode type input protection circuit 4 includes a PN junction diode D1 connected in the forward direction between an internal node 5 and a power supply node PS3, and a PN junction diode D2 connected in reverse direction between internal node 5 and the ground node. Power supply node PS3 of diode type input protection circuit 4 and power supply node PS1 of input circuit 2 are connected to each other through a power supply line 6. A parasitic capacitance C1 is parasitically connected to power supply line 6, and there is a parasitic capacitance C2 on a power supply line 7 connected to power supply node PS2. Power supply lines 6 and 7 are separated from each other. When an input signal having relatively small amplitude such as an LVTTL (low voltage transistor-transistor-logic) is used as an input signal, power supply voltage Vddi for the input circuit is set at a value lower with respect to the power supply voltage Vdd of the internal circuitry. When the power supply voltage Vdd is 3.3 V, LVTTL has input high level voltage VIH of 2.0 V and an input low level voltage VIL of 0.8 V. In order to accurately determine the H and L levels of such a signal having small amplitude, the voltage level of power supply voltage Vddi of input circuit 2 is made lower than the power supply voltage Vdd of the internal circuitry.
Input circuit 2 is an input buffer circuit connected to input pad 1, of which total number is relatively small, and hence capacitance value of parasitic capacitance C1 connected to power supply line 6 is relatively small. In contrast, internal circuit 3 connected to power supply line 7 has a number of components, and capacitance value of parasitic capacitance C2 connected to internal power supply line 7 is relatively large.
Assume that a positive surge voltage is applied to input pad 1. The positive surge voltage is at a voltage level sufficiently higher than power supply voltage Vddi, so that diode D1 is rendered conductive and the surge voltage is transmitted from power supply node PS3 through power supply line 6 and power supply node PS1 to input circuit 2. The surge voltage is dissipated and consumed by the components included in input circuit 2, and the surge voltage is absorbed.
When the surge voltage is to be absorbed by power supply line 6, however, the surge voltage cannot entirely be absorbed by parasitic capacitance C1 as the capacitance value of parasitic capacitance C1 connected to power supply line 6 is small, and a high surge voltage is undesirably applied to the components of input circuit 2, damaging the components (transistors) included in input circuit 2.
Similarly, when a negative surge voltage generates on input pad 1, diode D2 is rendered conductive, and the negative surge voltage is absorbed by the ground line through the ground node of diode type input protection circuit 4. When the ground node of diode type input protection circuit 4 and the ground node of input circuit 2 are connected to each other by the ground line, the negative surge voltage cannot sufficiently be absorbed as the parasitic capacitance of the ground line is also small, and therefore, components of input circuit 2 are damaged by the negative surge voltage.
Therefore, even when input protection circuit 4 is provided, the surge voltage cannot effectively be absorbed, and hence input circuit 2 cannot sufficiently be protected against the surge voltage.
FIG. 2 shows another configuration of the conventional input protection circuit. In the configuration shown in FIG. 2, a PN junction diode D3 is connected in the forward direction between power supply line 6 of input circuit 2 and power supply line 7 of internal circuit 3. In the configuration shown in FIG. 2, when a positive surge voltage is applied, diode D1 is rendered conductive and the surge voltage is transmitted to power supply line 6. When the surge voltage cannot sufficiently be absorbed by parasitic capacitance C1, diode D3 is rendered conductive, the surge voltage is transmitted from power supply line 6 to power supply line 7, and the surge voltage is absorbed by parasitic capacitance C2 existing on power supply line 7. As internal circuit 3 has a number of components and parasitic capacitance C2 has large capacitance value, the surge voltage can be absorbed without damaging the components of internal circuit 3.
By connecting separately provided power supply lines 6 and 7 utilizing diode D3, absorbing path of the positive surge voltage is ensured, improving surge resistance. By providing similar configuration, a negative surge voltage absorbing path can also be formed for the negative surge voltage.
FIG. 3 is a schematic diagram representing a cross sectional structure of PN junction diode D3 shown in FIG. 2. Referring to FIG. 3, PN junction diode D3 includes an N well 11 formed at a surface of a P type semiconductor substrate 10, a high concentration P type impurity region 12 formed at a surface of N well 11, and a high concentration N type impurity region 13 formed spaced from impurity region 12 at the surface of N well 11.
Diode D3 utilizes a PN junction formed between P type impurity region 12 and N well 11. P type impurity region 12 is connected to power supply node PS1 applying power supply voltage Vddi, and impurity region 13 is connected to power supply node PS2 applying power supply voltage Vdd. N well 11 has low impurity concentration and relatively high resistance. The PN junction between P type impurity region 12 and the N well is connected in series with a well resistance R of N well 11. When the surge voltage is transmitted from input pad 1 through diode D1 and power supply line 6 to diode D3, it is necessary to transmit the surge voltage at high speed to power supply node PS2 using diode D3, so that the surge voltage is absorbed at high speed by parasitic capacitance C2 of power supply line 7 connected to power supply node PS2.
However, as well resistance R has high resistance value, the surge voltage cannot fully be transmitted from power supply node PS1 to power supply node PS2 (as there is a considerable voltage drop caused by well resistance R), and therefore the voltage level of the surge voltage at power supply node PS1 cannot sufficiently be lowered. Therefore, there is a case that a large surge voltage is applied to input circuit 2 connected to power supply node PS2, damaging input circuit 2.
In order to eliminate the disadvantageous effect of well resistance R and to transmit the large surge voltage from power supply node PS1 to power supply node PS2 at high speed, it is necessary to enlarge the size (width) of diode D3 so as to lower the equivalent resistance value of well resistance R from power supply node PS1 to power supply node PS2. In that case, the size of PN junction diode D3 increases, and the area occupied by diode D3 increases. Further, when internal power supply lines 6 and 7 are not adjacent to each other and not parallel to each other, it is necessary to connect PN junction diode D3 between power supply lines 6 and 7 by using a lead line. Therefore, unless there is sufficient free area, layout of diode D3 with margin is difficult, which means that it is difficult to implement a surge voltage resistant circuit suitable for higher degree of integration.
An object of the present invention is to provide a semiconductor circuit device allowing improvement of surge resistance without increasing occupation area.
Another object of the present invention is to provide a semiconductor circuit device free of any restriction in position of laying-out a diode element for transmitting inter power supply surge voltage.
A further object of the present invention is to provide a multi-power source semiconductor circuit device in which the surge voltage is surely absorbed.
According to a first aspect, the present invention provides a semiconductor circuit device including a surge resistance enhancing element coupled between first and second power source lines and transmitting the surge voltage generated on the first power source line to the second power source line. The surge resistance enhancing element includes a buried layer of a second conductivity type formed in a substrate region of a first conductivity type, and a well of the second conductivity type formed at the surface of the buried layer. The bottom portion of the well is in contact with the surface of the buried layer.
The semiconductor circuit device in accordance with the first aspect further includes a first impurity region of the first conductivity type formed at the surface of the well and electrically connected to the first power source line, and a second impurity region of the second conductivity type formed apart from the first impurity region at the well surface and electrically connected to the second power source line.
According to a second aspect, the present invention provides a semiconductor circuit device including a first power source line formed extending continuously in the shape of a loop along the periphery of a rectangular region of the semiconductor substrate and transmitting a first power source voltage, an input circuit coupled to the first power source line and generating an internal signal in accordance with a signal applied to an input node, a second power source line formed extending in the shape of a loop along the periphery of the rectangular region of the semiconductor substrate and transmitting a second power source voltage, and a plurality of diode elements coupled parallel to each other between the first and second power source lines.
According to a third aspect, the present invention provides a semiconductor circuit device including a first power source line transmitting a first power source voltage, a second power source line provided separate from the first power source line and transmitting a second power source voltage, a third power source line provided separate from the first power source line and transmitting a third power source voltage, an input circuit operating using the first power source voltage of the first power source line as one operational power supply voltage and generating an internal signal in accordance with a signal applied to an input node, first internal circuitry receiving as one operational power source voltage the second power source voltage on the second power source line and performing a prescribed internal operation, and second internal circuitry receiving as one operational power supply voltage, the third power source voltage on the third power source line and performing a prescribed operation. In operation, the second internal circuitry consumes more current than the first internal circuitry in operation.
The semiconductor circuit device in accordance with the third aspect of the present invention further includes a diode element coupled between the first and second power source lines.
As the surge resistance enhancement element for transmitting the surge voltage between power source lines is formed in the well region and the buried layer, the buried layer reduces equivalently the well resistance, and reduces serial parasitic resistance of the PN junction diode element, so that the surge voltage can be transmitted at high speed from the first to the second power source line, and hence the surge voltage can efficiently be absorbed.
Further, as the first and second power source lines are arranged along the periphery of the rectangular region of the semiconductor substrate in the shape of loops and the diode element for transmitting surge voltage is arranged between the first and second power source lines, the first and second power source lines are arranged parallel to each other over a long distance, and it becomes possible to arrange the diode element to be overlapping on the first and second power source lines, which facilitates layout and allows increase in size (width) of the diode element. Therefore, the surge voltage can be transmitted efficiently.
Further, as a plurality of diode elements are provided, it is possible to efficiently transmit the surge voltage from the first power source line to the second power source line regardless of the position where the surge voltage generates. Therefore, the surge voltage resistance becomes less dependent on locations.